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個人簡介

蔡爍，男，博士，教授，博士生導師，湖南省普通高校青年骨干教師。中國計算機學會高級會員，中國計算機學會容錯計算專委會執行委員，湖南省計算機學會理事。2004年于浙江大學信息工程專業獲工學學士學位，2007年于湖南大學信號與信息處理專業獲工學碩士學位，2015年于湖南大學計算機科學與技術專業獲工學博士學位。從事宇航級集成電路抗輻射加固、電路系統可靠性評估、近似計算與人工智能等領域的研究。主持國家自然科學基金面上項目、青年基金項目、湖南省杰出青年基金項目等，在IEEE TVLSI、IEEE TCASⅡ、IEEE TNSE、Integration、JETTA、計算機學報、電子學報、電子與信息學報、ATS、ITC-Asia、CCF-DAC等國內外重要學術期刊和會議上發表論文40余篇。

招生方向：電子科學與技術博士和碩士（電路與系統方向），電子信息專業碩士。

主要研究領域

集成電路抗輻射加固設計、容錯計算、近似計算、人工智能、電路系統可靠性。

教學情況

主講《電路分析基礎》、《模擬電子電路》、《數字電路與邏輯設計》等課程。

科研項目

[1]主持國家自然科學基金面上項目：基于相關性分離的邏輯電路失效率高效分析與敏感目標精準定位，2022-2025；

[2]主持國家自然科學基金青年基金項目：邏輯級破解納米集成電路軟錯誤可靠性評估難題的新方法，2018-2020；

[3]主持湖南省自然科學基金杰出青年基金項目：空間輻射環境下納米集成電路可靠性評估與加固設計，2022-2024；

[4]主持湖南省自然科學基金面上項目：面向邏輯級超大規模集成電路軟錯誤率分析方法研究，2020-2022；

[5]主持湖南省教育廳重點項目：空間輻射環境下納米集成電路瞬態故障分析與可靠性評估，2019-2021；

[6]主持湖南省水利科技項目：大壩病害快速診斷與動態風險控制決策研究，2020-2022。

代表性論文

[1]Shuo Cai*, Xinjie Liang, Zhu Huang, Weizheng Wang, Fei Yu. Low Power and High Speed SRAM Cells with Double-Node Upset Self-Recovery for Reliable Applications. IEEE Transactions on Very Large Scale Integration Systems. 2025, 33(2): 475-487

[2]Shuo Cai, Huixin Gao, Jie Zhang, Ming Peng*. A self-attention-LSTM method for dam deformation prediction based on CEEMDAN optimization[J]. Applied Soft Computing. 2024(7): 111615

[3]Shuo Cai*, Xinjie Liang, Yan Wen, Fei Yu, Lairong Yin. A radiation-hardened 20T SRAM Cell with high reliability and low power consumption. 2024 IEEE International Test Conference in Asia (ITC-Asia). Changsha, China, 2024, 8. 18-20: 1-6

[4]蔡爍*, 何輝煌, 余飛, 尹來容, 劉洋. 基于相關性分離的邏輯電路敏感門定位算法. 電子與信息學報. 2024, 46(1): 362-372

[5]Shuo Cai*, Yan Wen, Caicai Xie, Weizheng Wang, Fei Yu. Low-power and high-speed SRAM Cells for Double-Node-Upset Recovery. Integration, the VLSI Journal. 2023, 91:1-9

[6]Shuo Cai*, Yan Wen, Jiangbiao Ouyang, Weizheng Wang, Fei Yu, Bo Li. A Highly Reliable and Low-Power Cross-Coupled 18T SRAM Cell. Microelectronics Journal. 2023, 134:105729:1-7

[7]Shuo Cai, Tingyu Luo, Fei Yu*, Pradip Kumar Sharma, Weizheng Wang, Lairong Yin. Reliability Analysis of Correlated Competitive and Dependent Components Considering Random Isolation Times. CMC: Computer, Materials & Continua. 2023, 76(3): 2763-2777

[8]Shuo Cai*, Jiangbiao Ouyang, Yan Wen, Weizheng Wang, Fei Yu. A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design. 2023 IEEE 32nd Asian Test Symposium(ATS), Beijing, China, 2023,10.14-17: 1-5

[9]Shuo Cai*, Caicai Xie, Yan Wen, Weizheng Wang, Fei Yu, Lairong Yin. Four-input-C-element-based Multiple-Node-Upset-Self-Recoverable Latch Designs. Integration, the VLSI Journal. 2023, 90:11-21

[10]Shuo Cai*, Binyong He, Sicheng Wu, Jin Wang, Weizheng Wang, Fei Yu. An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation. Journal of Electronic Testing-Theory and Applications. 2022, 38(2): 165-180

[11]Shuo Cai*, Sicheng Wu, Weizheng Wang, Fei Yu, Lairong Yin. Sensitive Vector Search for Logic Circuit Failure Probability based on Improved Adaptive Cuckoo Algorithm. Journal of Semiconductor Technology and Science. 2022, 22(2): 69-83

[12]Fei Yu, Xinxin Kong, Huifeng Chen, Qiulin Yu, Shuo Cai*, Yuanyuan Huang, Sichun Du. A 6D Fractional-Order Memristive Hopfield Neural Network and its Application in Image Encryption. Frontiers in Physics. 2022, 10: 847385, 1-14

[13]Fei Yu, Huifeng Chen, Xinxin Kong, Qiulin Yu, Shuo Cai*, Yuanyuan Huang, Sichun Du. Dynamic Analysis and Application in Medical Digital Image Watermarking of a New Multi-scroll Neural Network with Quartic Nonlinear Memristor. European Physical Journal Plus. 2022, 137(4): 434

[14]Shuo Cai*, Caicai Xie, Yan Wen, Weizheng Wang. A Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Design. 5th IEEE International Test Conference in Asia, ITC-Asia 2021. Shanghai,China,2021

[15]Shuo Cai*, Binyong He, Weizheng Wang, et al. Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults. Journal of Electronic Testing-Theory and Applications. 2020, 36(4): 469-483

[16]Shuo Cai*, Binyong He, Sicheng Wu, et al. An Accurate and Efficient Approach for Estimating the Failure Probability of Logic Circuits, 2020 CCF Integrated Circuit Design and Automation Conference, 2020: 1-15

[17]Shuo Cai*, Weizheng Wang, Fei Yu, Binyong He. Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits. Journal of Electronic Testing - Theory and Applications. 2019, 35(2): 163-172

[18]蔡爍*,鄺繼順,張亮,劉鐵橋,王偉征.基于差錯傳播概率矩陣的時序電路軟錯誤可靠性評估.計算機學報. 2015, 38(5): 923-931

[19]蔡爍*,鄺繼順,劉鐵橋,凌純清,尤志強.基于伯努利分布的邏輯電路可靠度計算方法.電子學報. 2015, 43(11)：2292-2297

[20]蔡爍*,鄺繼順,劉鐵橋,王偉征.考慮信號相關性的邏輯電路可靠度計算方法.電子學報.2014, 42(8): 1660-1664

聯系方式

E-mail: [email protected]