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1、個人基本信息：

姓  名：蔡爍

性  別：男

出生年月：1982年10月

技術職稱：教授

畢業(yè)院校：湖南大學

學歷（學位）：博士

所在學科：計算機科學與技術、信息與通信工程

研究方向：容錯計算、近似計算、電路系統(tǒng)可靠性、集成電路抗輻射加固設計、人工智能、物聯(lián)網(wǎng)可靠性

2、教育背景：

2000.9-2004.6

浙江大學

信息工程，學士

2004.9-2007.6

湖南大學

信號與信息處理，碩士

2010.9-2015.4

湖南大學

計算機科學與技術，博士

3、 目前研究領域：

容錯計算、近似計算、電路系統(tǒng)可靠性、集成電路抗輻射加固、人工智能、物聯(lián)網(wǎng)可靠性。

4、已完成或已在承擔的主要課題：

[1] 國家自然科學基金面上項目：基于相關性分離的邏輯電路失效率高效分析與敏感目標精準定位，2022.1-2025.12，No：62172058，主持，在研；

[2] 湖南省自然科學基金杰出青年基金項目：空間輻射環(huán)境下納米集成電路可靠性評估與加固設計，2022.1-2024.12，No：2022JJ10052，主持，在研；

[3] 湖南省自然科學基金面上項目：面向邏輯級超大規(guī)模集成電路軟錯誤率分析方法研究，2020.1-2022.12，主持，No：2020JJ4622，主持，已完成；

[4] 國家自然科學基金青年項目：邏輯級破解納米集成電路軟錯誤可靠性評估難題的新方法，2018.1-2020.12，No：61702052，主持，已完成；

[5] 湖南省教育廳重點項目：空間輻射環(huán)境下納米集成電路瞬態(tài)故障分析與可靠性評估，2019.9-2021.8，No：18A137，主持，已完成；

[6] 湖南省水利科技項目：大壩病害快速診斷與動態(tài)風險控制決策研究，2020.7-2022.6，No：XSKJ2019081-47，主持，已完成。

6、已發(fā)表的學術論文：

[1] Shuo Cai*, Xinjie Liang, Zhu Huang, Weizheng Wang, Fei Yu. Low Power and High Speed SRAM Cells with Double-Node Upset Self-Recovery for Reliable Applications. IEEE Transactions on Very Large Scale Integration Systems. 2025, 33(2): 475-487

[2] Shuo Cai, Huixin Gao, Jie Zhang, Ming Peng*. A self-attention-LSTM method for dam deformation prediction based on CEEMDAN optimization[J]. Applied Soft Computing. 2024(7): 111615

[3] Shuo Cai*, Xinjie Liang, Yan Wen, Fei Yu, Lairong Yin. A radiation-hardened 20T SRAM Cell with high reliability and low power consumption. 2024 IEEE International Test Conference in Asia (ITC-Asia). Changsha, China, 2024, 8. 18-20: 1-6

[4] 蔡爍*, 何輝煌, 余飛, 尹來容, 劉洋. 基于相關性分離的邏輯電路敏感門定位算法. 電子與信息學報. 2024, 46(1): 362-372

[5] Shuo Cai*, Yan Wen, Caicai Xie, Weizheng Wang, Fei Yu. Low-power and high-speed SRAM Cells for Double-Node-Upset Recovery. Integration, the VLSI Journal. 2023, 91:1-9

[6] Shuo Cai*, Yan Wen, Jiangbiao Ouyang, Weizheng Wang, Fei Yu, Bo Li. A Highly Reliable and Low-Power Cross-Coupled 18T SRAM Cell. Microelectronics Journal. 2023, 134:105729:1-7

[7] Shuo Cai, Tingyu Luo, Fei Yu*, Pradip Kumar Sharma, Weizheng Wang, Lairong Yin. Reliability Analysis of Correlated Competitive and Dependent Components Considering Random Isolation Times. CMC: Computer, Materials & Continua. 2023, 76(3): 2763-2777

[8] Shuo Cai*, Jiangbiao Ouyang, Yan Wen, Weizheng Wang, Fei Yu. A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design. 2023 IEEE 32nd Asian Test Symposium(ATS), Beijing, China, 2023,10.14-17: 1-5

[9] Shuo Cai*, Caicai Xie, Yan Wen, Weizheng Wang, Fei Yu, Lairong Yin. Four-input-C-element-based Multiple-Node-Upset-Self-Recoverable Latch Designs. Integration, the VLSI Journal. 2023, 90:11-21

[10] Shuo Cai*, Binyong He, Sicheng Wu, Jin Wang, Weizheng Wang, Fei Yu. An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation. Journal of Electronic Testing-Theory and Applications. 2022, 38(2): 165-180

[11] Shuo Cai*, Sicheng Wu, Weizheng Wang, Fei Yu, Lairong Yin. Sensitive Vector Search for Logic Circuit Failure Probability based on Improved Adaptive Cuckoo Algorithm. Journal of Semiconductor Technology and Science. 2022, 22(2): 69-83

[12] Fei Yu, Xinxin Kong, Huifeng Chen, Qiulin Yu, Shuo Cai*, Yuanyuan Huang, Sichun Du. A 6D Fractional-Order Memristive Hopfield Neural Network and its Application in Image Encryption. Frontiers in Physics. 2022, 10: 847385, 1-14

[13] Fei Yu, Huifeng Chen, Xinxin Kong, Qiulin Yu, Shuo Cai*, Yuanyuan Huang, Sichun Du. Dynamic Analysis and Application in Medical Digital Image Watermarking of a New Multi-scroll Neural Network with Quartic Nonlinear Memristor. European Physical Journal Plus. 2022, 137(4): 434

[14] Shuo Cai*, Caicai Xie, Yan Wen, Weizheng Wang. A Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Design. 5th IEEE International Test Conference in Asia, ITC-Asia 2021. 中國上海, 2021

[15] Shuo Cai*, Binyong He, Weizheng Wang, et al. Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults. Journal of Electronic Testing-Theory and Applications. 2020, 36(4): 469-483

[16] Shuo Cai*, Binyong He, Sicheng Wu, et al. An Accurate and Efficient Approach for Estimating the Failure Probability of Logic Circuits, 2020 CCF Integrated Circuit Design and Automation Conference, 2020: 1-15

[17] Shuo Cai*, Weizheng Wang, Fei Yu, Binyong He. Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits. Journal of Electronic Testing - Theory and Applications. 2019, 35(2): 163-172

[18] Shuo Cai*, Fei Yu, Yiqun Yang. Analysis of SET Pulses Propagation Probabilities in Sequential Circuits, 2017 the 4th International Conference on Advances in Electronics Engineering, 2017: 1-6

[19] Shuo Cai*, Yinbo Zhou, Peng Liu, Fei Yu, Wei Wang. A Novel Test Data Compression Approach Based on Bit Reversion. IEICE Electronics Express. 2017, 14(13): 1-11

[20] Shuo Cai*, Fei Yu, Weizheng Wang, Tieqiao Liu, Peng Liu, Wei Wang. Reliability Evaluation of Logic Circuits Based on Transient Faults Propagation Metrics. IEICE Electronics Express. 2017, 14(7): 1-7

[21] Cai Shuo, Kuang Jishun*, Liu Tieqiao, Wang Weizheng. Soft Error Susceptibility Analysis for Sequential Circuit Elements Based on EPPMs. Journal of Semiconductor Technology and Science. 2015, 15(2): 168-176

[22] 蔡爍*,鄺繼順,張亮,劉鐵橋,王偉征.基于差錯傳播概率矩陣的時序電路軟錯誤可靠性評估.計算機學報. 2015, 38(5): 923-931

[23] 蔡爍*,鄺繼順,劉鐵橋,凌純清,尤志強.基于伯努利分布的邏輯電路可靠度計算方法.電子學報. 2015, 43(11)：2292-2297

[24] 蔡爍*,鄺繼順,劉鐵橋,王偉征.考慮信號相關性的邏輯電路可靠度計算方法.電子學報.2014, 42(8): 1660-1664

[25] 蔡爍*,鄺繼順,劉鐵橋,周穎波.一種高效的門級電路可靠度估算方法.電子與信息學報. 2013, 35(5): 1262-1266

[26] 蔡爍*,胡航滔,王威.基于深度卷積網(wǎng)絡的高分遙感圖像語義分割.信號處理, 2019. 35(12): 2010-2016

7、 所獲學術榮譽及學術影響：

[1] 湖南省杰出青年基金項目獲得者

[2] 湖南省青年骨干教師

[3] 中國計算機學會高級會員

[4] 中國計算機學會容錯計算專委會執(zhí)行委員

[5] 中國通信學會會員

[6] 湖南省計算機學會理事

[7] 湖南省人工智能學會會員